Switch capacitor filters, capacitor D to A and A to D converters, and capacitor controlled gain stages which are in common use today require precise ratio matched capacitors. The difficulty of making such ratio matched capacitors with current MOS integrated circuit technology is well known. One of the primary difficulties encountered, which is the subject of the present invention, is the change in ratio of matched capacitors due to the effects of over or under exposure during photoresist processing or to over or under etching of the individual capacitor plates. Both of these effects can substantially vary the capacitive ratio of these matched capacitors from their nominal design values.
One method of substantially reducing these effects is to arrange the capacitor geometry so that the ratios of the respective capacitor areas to periphery lengths are equal. While this method is effective, it requires considerable skill on the part of the designer to lay out this geometry. Trial and error techniques are frequently employed with mixed results. Another method of reducing these effects is through the use of so called "unit capacitors". The theory is that each of the matched capacitors is composed of a number of identical unit capacitors which are equally affected by over or under exposure of the photoresist, or to over or under etching. Therefore, each of the matched capacitors will be affected in proportion to the number of unit capacitors contained therein thereby retaining a fixed ratio of capacitance between the matched capacitors. Examples of the use of such unit capacitors may be found in J. L. McGreary et al., IEEE J, Solid-State Circuits, Part 1, Vol. SC-10, pp. 371-379, Dec. 1975 and in D. L. Allstat et al., Proceedings IEEE, Technological Design Considerations for Monolithic MOS Switched-Capacitor Filtering Systems, Vol. 71, No. 8, pp. 967-986, Aug. 1983.
Needless to say, the identical unit capacitors must be interconnected in parallel by some means, usually a metal conductor which is formed on the surface of the device. Substantial parasitic capacitances occur where the metal conductors cross the spaces between the unit capacitor elements. Where the conductor is on the same level as the capacitor plates, which is usually the case when the top plates are metal, the effect on the matched capacitor ratio can be on the order of 0.98 percent. Even where an extra thick oxide layer is used to raise the level of the conductor above the substrate, the effect on the matched capacitor ratio can be as high as 0.14 percent. Both of these are intolerable amounts in certain circuit applications.
Another source of error in the capacitance ratio stems from the need to account for a non-integer amount of capacitance when using the unit capacitors. The usual procedure is to simply increase or reduce the size of one of the unit capacitors. This in turn causes an error in the area to periphery ratio of the capacitor which, as described above, can result in an error in the matched capacitor ratio.
What is needed is an easily utilized geometry for matched capacitors which eliminates parasitic capacitance due to unit capacitor interconnect conductors and which permits non-integer amounts of capacitance while maintaining a desired capacitor area to periphery ratio.